Memory units, such as random access memory (RAM), are common components in computer systems (e.g. processors). Accordingly, verifying the operation of memory units in a hardware design is an important task. However, different memory units can support or implement one or more optional features, such as, multiple access ports, partial reads/writes, clock gating, and pipelining; which makes it difficult to design a generic system and/or method to verify the operation of memory units.
The embodiments described below are provided by way of example only and are not limiting of implementations which solve any or all of the disadvantages of known memory unit verification systems.